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RISControllerTM Embedded 64-bit Microprocessor, based on RISCore4000TM
Features
High performance 64-bit microprocessor, based on the RISCore4000 - Minimized branch and load delays, through streamlined 5-stage scalar pipeline. - Single and double precision floating-point unit - 125 peak MFLOP/s at 250 MHz - 330 Dhrystone MIPS at 250 MHz - Flexible RC4700-compatible MMU - Joint TLB on-chip, for virtual-to-physical address mapping On-chip two-way set associative caches - 16KB instruction cache (I-cache) - 16KB data cache (D-cache) Optional I-cache and D-cache locking (per set), provides improved real-time support Enhanced, flexible bus interface allows simple, low-cost design - 64-bit Bus Interface option, 1000MB/s bandwidth support - 32-bit Bus Interface option, 500MB/s bandwidth support - SDRAM timing protocol, through delayed data in write cycles - RC4000/RC5000 family bus-protocol compatibility - Bus runs at fraction of pipeline clock (1/2 to 1/8) Implements MIPS-III Instruction Set Architecture (ISA) 3.3V core with 3.3V I/O

RC64474TM RC64475TM
Software compatible with entire RISController Series of Embedded Microprocessors Industrial temperature range support Active power management - Powers down inactive units, through sleep-mode feature 100% pin compatibility between RC64574, RC64474 and RC4640 100% pin compatibility between RC64575, RC64475 and RC4650 RC64474 available in 128-pin QFP package, for 32-bit only systems RC64475 available in 208-pin QFP package, for full 64/32 bit systems Simplified board-level testing, through full Joint Test Action Group (JTAG) boundary scan Windows(R) CE compliant
Block diagram
330 MIPS 64-bit RISCore4000 CPU Core System Control Coprocessor (CPO) 125 MFLOPS Single/Double Precision FPA
Control Bus Data Bus Instruction Bus
16KB Instruction Cache (Lockable)
32-/64-bit Synchronized System Interface
16KB Data Cache (Lockable)
The IDT logo is a trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
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DSC 4952
RC64474TM RC64475TM
Device Overview1
Extending Integrated Device Technology's (IDT) RISCore4000 based choices (see Table 1), the RC64474 and RC64475 are high performance 64-bit microprocessors targeted towards applications that require high bandwidth, real-time response and rapid data processing and are ideal for products ranging from internetworking equipment (switches, routers) to multimedia systems such as web browsers, set-top boxes, video games, and Windows(R)CE based products. These processors are rated at 330 Dhrystone MIPS and 125 Million floating point operations per second, at 250 MHz. The internal cache bandwidth for these devices is over 3GB/second. The 64-bit external bus bandwidth is at more than 1000MB/s, and the 32-bit external bus bandwidth is at 500MB/s. The RC64474 is packaged in a 128-pin QFP footprint package and uses a 32-bit external bus, offering the ideal combination of 64-bit processing power and 32-bit low-cost memory systems. The RC64475 is packaged in a 208-pin QFP footprint package and uses the full 64-bit external bus. The RC64475 is ideal for applications requiring 64-bit performance and 64-bit external bandwidth. IDT's RISCore4000 is a 250MHz 64-bit execution core that uses a 5-stage pipeline, eliminating the "issue restrictions" associated with other more complex pipelines. The RISCore4000 implements the MIPS-III Instruction Set Architecture (ISA) and is upwardly compatible with applications that run on earlier generation parts. Implementation of the MIPS-III architecture results in 64-bit operations, improved performance for commonly used code sequences in
1. Detailed system operation information is provided in the RC64474/RC64475 user's manual.
operating system kernels, and faster execution of floating-point intensive applications. The RISCore4000 integer unit implements a load/store architecture with single cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The ALU consists of the integer adder and logic unit. The adder performs address calculations in addition to arithmetic operations, and the logic unit performs all of the processor's logical and shift operations. Each unit is highly optimized and can perform an operation in a single pipeline cycle. Both 32- and 64-bit data operations are performed by the RISCore4000, utilizing 32 general purpose 64-bit registers (GPR) that are used for integer operations and address calculation. A complete on-chip floating-point co-processor (CP1), which includes a floating-point register file and execution units, forms a "seamless" interface, decoding and executing instructions in parallel with the integer unit. CP1's floating-point execution units support both single and double precision arithmetic--as specified in the IEEE Standard 754-- and are separated into a multiply unit and a combined add/convert/ divide/square root unit. Overlap of multiplies and add/subtract is supported, and the multiplier is partially pipelined, allowing the initiation of a new multiply instruction every fourth pipeline cycle. The floating-point register file is made up of thirty-two 64-bit registers. The floating-point unit can take advantage of the 64-bit wide data cache and issue a co-processor load or store doubleword instruction in every cycle. The RISCore4000's system control coprocessor (CP0) registers are also incorporated on-chip and provide the path through which the virtual memory system's page mapping is examined and changed, exceptions are handled, and any operating mode selections are controlled.
RISCore4000/RISCore5000 Family of Socket Compatible Processors
32-bit Processors RC4640
CPU Performance FPA Caches External Bus
64-bit RISCore4000 w/ DSP extensions >350MIPS 89 mflops, single precision only 8kB/8kB, 2-way, lockable by set 32-bit
64-bit Processors RC64574 RC4650
64-bit RISCore4000 w/ DSP extensions >350MIPS 89 mflops, single precision only 8kB/8kB, 2-way, lockable by set 32- or 64-bit
RC64474
64-bit RISCore4000 >330MIPS 125 mflops, single and double precision 16kB/16kB, 2-way, lockable by set 32-bit, Superset pin compatible w/RC4640 3.3V 180-250 MHz 128 QFP 96 page TLB Cache locking, JTAG, syncDRAM mode, 32bit external bus
RC64475
64-bit RISCore4000 >330MIPS 125 mflops, single and double precision 16kB/16kB, 2-way, lockable by set 32-or 64-bit, Superset pin compatible w/ RC4650 3.3V 180-250 MHz 208 QFP 96 page TLB Cache locking, JTAG, syncDRAM mode, 3264- bit bus option
RC64575
64-bit RISCore5000 w/ DSP extensions >440MIPS 666 mflops, single and double precision 32kB/32kB, 2-way, lockable by line 32-or 64-bit, Superset pin compatible w/ RC4650, RC64475 2.5V 200-333 MHz 208 QFP 96 page TLB Cache locking, JTAG, syncDRAM mode, 3264- bit bus option
64-bit RISCore5000 w/ DSP extensions >440MIPS 666 mflops, single and double precision 32kB/32kB, 2-way, lockable by line 32-bit, Superset pin compatible w/RC4640, RC64474 2.5V 200-333 MHz 128 QFP 96 page TLB Cache locking, JTAG, syncDRAM mode, 32bit external bus
Voltage Frequencies Packages MMU Key Features
3.3V 100-267 MHz 128 PQFP Base-Bounds Cache locking, onchip MAC, 32-bit external bus
3.3V 100-267 MHz 208 QFP Base-Bounds Cache locking, onchip MAC, 32-bit & 64 bit bus option
Table 1 RISCore4000/RISCore5000 Processor Family 2 of 25 April 10, 2001
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A secure user processing environment is provided through the user, supervisor, and kernel operating modes of virtual addressing to system software. Bits in a status register determine which of these modes is used. If configured for 64-bit virtual addressing, the virtual address space layout becomes an upwardly compatible extension of the 32-bit virtual address space layout. Figure 1 is an illustration of the address space layout for the 32-bit virtual address operation.
can be locked into the TLB and avoid being randomly replaced, which facilitates the design of real-time systems, by allowing deterministic access to critical software. The TLB also contains information to control the cache coherency protocol, and cache management algorithm for each page. However, hardware-based cache coherency is not supported. The RC64474 and RC64475 enhance IDT's entire RISCore4000 series through the implementation of features such as boundary scan, to facilitate board level testing; enhanced support for SyncDRAM, to simplify system implementation and improve performance. The RC64474/475 processors offer a direct migration path for designs based on IDT's RC4640/RC4650 processors2, through full pin and socket compatibility. Also, full 64-bit-family software and busprotocol compatibility ensures the RC64474/475 access to a robust development tools infrastructure, allowing quicker time to market. Development Tools An array of hardware and software tools is available to assist system designers in the rapid development of RC64474/475 based systems. This accessibility allows a wide variety of customers to take full advantage of the device's high-performance features while addressing today's aggressive time-to-market demands.
0xFFFFFFFF 0xE0000000 0xDFFFFFFF
Kernel virtual address space (kseg3) Mapped, 0.5GB Supervisor virtual address space (sseg) Mapped, 0.5GB Uncached kernel physical address space (kseg1) Unmapped, 0.5GB Cached kernel physical address space (kseg0) Unmapped, 0.5GB
0xC0000000 0xBFFFFFFF 0xA0000000 0x9FFFFFFF
0x80000000 0x7FFFFFFF
Cache Memory
To keep the RC64474 and RC64475's high-performance pipeline full and operating efficiently, on-chip instruction and data caches have been incorporated. Each cache has its own data path and can be accessed in the same single pipeline clock cycle. The 16KB two-way set associative instruction cache (I-cache) is virtually indexed, physically tagged, and word parity protected. Because this cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access, further increasing performance by allowing both operations to occur simultaneously. The instruction cache provides a peak instruction bandwidth of 1000MB/sec at 250MHz. The 16KB two-way set associative data cache (D-cache) is byte parity protected and has a fixed 32-byte (eight words) line size. Its tag is protected with a single parity bit. To allow simultaneous address translation and data cache access, the D-cache is virtually indexed and physically tagged. The data cache can provide 8 bytes each clock cycle, for a peak bandwidth of 2GB/sec. To lock critical sections of code and/or data into the caches for quick access, a "cache locking" feature has been implemented. Once enabled, a cache is said to be locked when a particular piece of code or data is loaded into the cache and that cache location will not be selected later for refill by other data. This feature locks a set (8KB) of Instructions and/or Data. Table 2 lists the RC64474/475 Instruction and data cache attributes.
2. To ensure socket compatibility, refer to Table 8 and Table 9 at back of data sheet.
User virtual address space (useg) Mapped, 2.0GB
0x00000000 Figure 1 Kernel Mode Virtual Addressing (32-bit Mode)
The RC64474/RC64475's Memory Management Unit (MMU) controls the virtual memory system's page mapping and consists of a translation lookaside buffer (TLB) used for the virtual memory-mapping subsystem. This large, fully associative TLB maps 96 virtual pages to their corresponding physical addresses. The TLB is organized as 48 pairs of even-odd entries and maps a virtual address and address space identifier into the large, 64GB physical address space. To assist in controlling the amount of mapped space and the replacement characteristics of various memory regions, two mechanisms are provided. First, the page size can be configured on a per-entry basis, to map a page size of 4KB to 16MB (in increments of 4x). The second mechanism controls the replacement algorithm, when a TLB miss occurs. A random replacement algorithm is provided to select a TLB entry to be written with a new mapping; however, the processor provides a mechanism whereby a system specific number of mappings
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Characteristics Size Organization Line size read unit write policy Line transfer order Miss restart after transfer of: Parity Cache locking
Instruction 16KB 2-way set associative 32B 32-bits na sub-block order, for refill entire line per-word per set 16KB
Data
2-way set associative 32B 64-bits write-back, write-through with or without write-allocate sub-block order, for load sequential order, for store miss word per-byte per set
A boot-time mode control interface initializes fundamental processor modes. The boot-time mode control interface is a serial interface that operates at a very low frequency (MasterClock divided by 256). This low-frequency operation allows the initialization information to be kept in a low-cost EPROM; alternatively, the twenty-or-so bits could be generated by the system interface ASIC or a simple PAL. The boottime serial stream and configuration options are listed in Table 3. The clocking interface allows the CPU to be easily mated with external reference clocks. The CPU input clock is the bus reference clock and can be between 25 and 125MHz. An on-chip phase-lockedloop (PLL) generates the pipeline clock (PClock) through multiplication of the system interface clock by values of 2,3,4,5,6,7 or 8, as defined at system reset. This allows the pipeline clock to be implemented at a significantly higher frequency than the system interface clock. The RC64474/475 support single data (one to eight bytes) and 8-word block transfers on the SysAD bus. The RC64474/475 implement additional write protocols that double the effective write bandwidth. The write re-issue has a repeat rate of 2 cycles per write. Pipelined writes have the same 2-cycle per write repeat rate, but can issue an additional write after WrRdy* deasserts. Choosing a 32- or 64-bit wide system interface dictates whether a cache line block transaction requires 4 double word data cycles or 8 single word cycles as well as whether a single data transfer--larger than 4 bytes--must be divided into two smaller transfers. Board-level testing during Run-Time mode is facilitated through the full JTAG boundary scan facility. Six pins--TDI, TDO, TMS, TCK, TRST* and JTAG32*--have been incorporated to support the standard JTAG interface. System Enhancement To facilitate discrete interface to SDRAM, the RC64474/475 bus interface is enhanced during write cycles with a programmable delay that is inserted between the write address and the write data (for both block and non-block writes). The bus delay can be defined as 0 to 7 MasterClock cycles and is activated and controlled through mode bit (17:15) settings selected during the reset initialization sequence. The `000' setting provides the same write operations timing protocol as the RC4640, RC4650, and RC5000 processors.
Table 2 RC64474/RC64475 Instruction/Data Cache Attributes
System Interfaces
The RC64475 supports a 64-bit system interface that is bus compatible with the RC4650 and RC64575 system interface. The system interface consists of a 64-bit Address/Data bus with 8 check bits and a 9-bit command bus that is parity protected. During 64-bit operation, RC64475 system address/data (SysAD) transfers are protected with an 8-bit parity check bus, SysADC. When initialized for 32-bit operation, the RC64475's SysAD can be viewed as a 32-bit multiplexed bus that is protected by 4 parity check bits. The RC64474 supports a 32-bit system interface that is bus compatible with the RC4640. During 32-bit operation, SysAD transfers are performed on a 32-bit multiplexed bus (SysAD 31:0) that is protected by 4 parity check bits (SysADC 6:0). Writes to external memory--whether they are cache miss writebacks, stores to uncached or write-through addresses--use the on-chip write buffer. The write buffer holds a maximum of four 64-bit addresses and 64-bit data pairs. The entire buffer is used for a data cache writeback and allows the processor to proceed in parallel with memory updates. Included in the system interface are six handshake signals: RdRdy*, WrRdy*, ExtRqst*, Release*, ValidOut*, and ValidIn*; six interrupt inputs, and a simple timing specification that is capable of transferring data between the processor and memory at a peak rate of 1000MB/sec. A boot-time selectable option to run the system interface as 32-bits wide--using basically the same protocols as the 64-bit system--is also supported.
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Serial Bit 255:18 17:15 Reserved
Description Must be 0 000 0 cycles 001 1 cycle 010 2 cycles 011 3 cycles 100 4 cycles 101 5 cycles 110 6 cycles 111 7 cycles
Value & Mode Setting
WAdrWData_Del Write address to write data delay in MasterClock cycles.(R)
14:13
Drv_Out output driver slew rate control. Bit 14 is MSB. Affects only non-clock outputs.
Output driver strength: 10 100% strength (fastest) 11 83% strength 00 67% strength 01 50% strength (slowest) 0 64-bit system interface 1 32-bit system interface 0 Enabled Timer Interrupt 1 Disabled Timer Interrupt 00 RC4x00 compatible 01 Reserved 10 Pipelined writes 11 Write re-issue Clock multiplier: 0 Multiply by 2 1 Multiply by 3 2 Multiply by 4 3 Multiply by 5 4 Multiply by 6 5 Multiply by 7 6 Multiply by 8 7 Reserved 0 Little endian 1 Big endian 64-bit: 9:15 Reserved 8 dxxxdxxxdxxxdxxx 7 ddxxxxxxddxxxxxx 6 dxxdxxdxxdxx 5 ddxxxxddxxxx 4 ddxxxddxxx 3 dxdxdxdx 2 ddxxddxx 1 ddxddx 0 dddd Must be zero Table 3 Boot-time Mode Stream 32-bit: 9:15 Reserved 8 wxxxwxxxwxxxwxxxwxxxwxxxwxxxwxxx 7 wwxxxxxxwwxxxxxxwwxxxxxxwwxxxxxx 6 wxxwxxwxxwxxwxxwxxwxxwxx 5 wwxxxxwwxxxxwwxxxxwwxxxx 4 wwxxxwwxxxwwxxxwwxxx 3 wxwxwxwxwxwxwxwx 2 wwxxwwxxwwxxwwxx 1 wwxwwxwwxwwx 0 AE wwwwwwww
12 11 10:9
System interface bus width TmrIntEn Disables the timer interrupt on Int*[5] Non-block write Selects non-block write type. Bit 10 is MSB.
7:5
Clock Multiplier MasterClock is multiplied internally to generate PClock
8 4:1
EndBit Specifies byte ordering Writeback data rate System interface data rate for block writes only: bit 4 is MSB
0
Reserved
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Power Management
Executing the WAIT instruction enables the processor to enter Standby mode. The internal clocks will shut down, thus freezing the pipeline. The PLL, internal timer, and some of the input pins (Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*) will continue to run. Once the CPU is in Standby Mode, any interrupt, including the internally generated timer interrupt, will cause the CPU to exit Standby Mode.
January 17, 2000: Added "with DSP extensions" in the CPU row under RC64574 and RC64575 columns in Table 1. Added "lockable by line" in the Caches row under RC64574 and RC64575 columns in Table 1. Revised Data Output and Data Output Hold rows in System Interface Parameters table. February 10, 2000: Revised values in Table 4, Thermal Resistance. Old values were: CA
Airflow (ft/min) 128 QFP 208 QFP 0 20 20 200 12 12 400 9 9 600 8 8 800 7 7 1000 6 6
Thermal Considerations
The RC64474/475 come in a QFP with a drop-in heat spreader and are guaranteed in a case temperature range of 0 to +85 C, for commercial temperature devices; - 40 to +85 for industrial temperature devices. The type of package, speed (power) of the device, and airflow conditions affect the equivalent ambient temperature conditions that will meet this specification. The equivalent allowable ambient temperature, TA, can be calculated using the thermal resistance from case to ambient (CA) of the given package. The following equation relates ambient and case temperatures: TA = TC - P * CA where P is the maximum power consumption at hot temperature, calculated by using the maximum ICC specification for the device. Typical values for CA at various airflows are shown in Table 4. Note that the RC64474/475 processors implement advanced power management, which substantially reduces the typical power dissipation of the device.
March 13, 2000: Replaced existing figure in Mode Configuration Interface Reset Sequence section with 3 reset figures. March 28, 2000: Removed the symbol tDZ from Figure 3. April 17, 2000: Changed VIH value in 200MHz column from 2.0V to 0.7VCC. April 10, 2001: In the Data Output and Data Output Hold categories of the System Interface Parameters table, changed values in the Min column for all speeds from 1.0 to 0. Deleted Output for Loading AC Testing diagram and added Output Loading for AC Timing diagram (Figure 8).
CA
Airflow (ft/min) 128 QFP 208 QFP 0 16 20 200 10 13 400 9 10 600 7 9 800 6 8 1000 5 7
Table 4 Thermal Resistance (CA) at Various Airflows
Data Sheet Revision History
December 1998: Changed ordering code on 128-pin package from DQ / DQI (Industrial) to DZ / DZI (Industrial). January 1999: Removed 5V tolerance capability and deleted 5V tolerant pin. February 1999: Changed the package drawings to reflect the new 208-pin DP (DPI) and 128-pin DZ (DZI) packages. May 1999: Removed "Preliminary" status from data sheet. Changes in DC Electrical Characteristics table. Changes in Pin Description table. Changes in Clock Parameters table. Changes in System Interface Parameters table. September 1999: Updated Revision History section.
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Pin Description Table
The following is a list of system interface pins available on the RC64474/475. Pin names ending with an asterisk (*) are active when low.
Pin Name System Interface ExtRqst* I External request An external agent asserts ExtRqst* to request use of the System interface. The processor grants the request by asserting Release*. Release interface In response to the assertion of ExtRqst* or a CPU read request, the processor asserts Release* and signals to the requesting device that the system interface is available. Read Ready The external agent asserts RdRdy* to indicate that it can accept a processor read request. Write Ready An external agent asserts WrRdy* when it can now accept a processor write request. Valid Input Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. Valid output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. System address/data bus A 64-bit address and data bus for communication between the processor and an external agent. During address phases only, SysAd(35:0) contains valid address information. The remaining SysAD(63:36) pins are not used. The whole 64-bit SysAD(63:0) may be used during the data transfer phase. In 32-bit mode and in the RC64474, SysAD(63:32) is not used, regardless of Endianness. A 32-bit address and data communication between processor and external agent is performed via SysAD(31:0). System address/data check bus An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles. In 32-bit mode and in the RC64474, SysADC(7:4) is not used. The SysADC(3:0) contains check bits for SysAD(31:0). System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. System Command Parity A single, even-parity bit for the Syscmd bus. This signal is always driven low. Type Description
Release*
O
RdRdy* WrRdy* ValidIn*
I I I
ValidOut*
O
SysAD(63:0)
I/O
SysADC(7:0)
I/O
SysCmd(8:0) SysCmdP Clock/Control Interface MasterClock
I/O I/O
I
Master Clock Master clock input establishes the processor and bus operating frequency. It is multiplied internally by 2,3,4,5,6,7,8 to generate the pipeline clock (PClock). This clock must be driven by 3.3V (Vcc) clock signals, regardless of the 5V tolerant pin setting. Quiet VCC for PLL Quiet VCC for the internal phase locked loop. Quiet VSS for PLL Quiet VSS for the internal phase locked loop.
VCCP VSSP Interrupt Interface Int*(5:0)
I I
I
Interrupt Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register. Table 5 Pin Descriptions (Page 1 of 2)
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RC64474TM RC64475TM Pin Name NMI* Initialization Interface VCCOk I VCC is OK When asserted, this signal indicates to the processor that the power supply has been above the Vcc minimum for more than 100 milliseconds and will remain stable. The assertion of VCCOk initiates the initialization sequence. Cold reset This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with MasterClock. Reset This signal must be asserted for any reset sequence. It can be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with MasterClock. Boot-mode clock Serial boot-mode data clock output at the system clock frequency divided by two hundred fifty-six. Boot-mode data in Serial boot-mode data input. I Type Description Non-maskable interrupt Non-maskable interrupt, ORed with bit 6 of the interrupt register.
ColdReset*
I
Reset*
I
ModeClock ModeIn JTAG Interface TDI
O I
I
JTAG Data In On the rising edge of TCK, serial input data are shifted into either the Instruction register or Data register, depending on the TAP controller state. JTAG Data Out On the falling edge of TCK, the TDO is serial data shifted out from either the instruction or data register. When no data is shifted out, the TDO is tri-stated (high impedance). JTAG Clock Input An input test clock used to shift into or out of the boundary-scan register cells. TCK is independent of the system and processor clock with nominal 40-60% duty cycle. JTAG Command Select The logic signal received at the TMS input is decoded by the TAP controller to control test operation. TMS is sampled on the rising edge of TCK. JTAG Reset The TRST* pin is an active-low signal used for asynchronous reset of the debug unit, independent of the processor logic. During normal CPU operation, the JTAG controller will be held in the reset mode, asserting this active low pin. When asserted low, this pin will also tristate the TDO pin. JTAG 32-bit scan This pin is used to control length of the scan chain for SYsAD (32-bit or 64-bit) for the JTAG mode. When set to Vss, 32-bit bus mode is selected. In this mode, only SysAD(31:0) are part of the scan chain. When set to Vcc, 64-bit bus mode is selected. In this mode, SysAD(63:0) are part of the scan chain. This pin has a built-in pull-down device to guarantee 32-bit scan, if it is left uncovered. JTAG VCC This pin has an internal pull-down to continuously reset the JTAG controller (if left unconnected) bypassing the TRst* pin. When supplied with Vcc, the TRst* pin will be the primary control for the JTAG reset. Table 5 Pin Descriptions (Page 2 of 2)
TDO
O
TCK
I
TMS
I
TRST*
I
JTAG32*
I
JR_Vcc
I
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Logic Diagram -- RC64474/RC64475
Figure 2 illustrates the direction and functional groupings for the processor signals.
Clock/Control Interface
MasterClock VCCP VSSP
64 8
9
SysAD(63:0) SysADC(7:0) SysCmd(8:0) SysCmdP
TDI Interface TDO TMS TRST* JTAG TCK JTag32* JR_Vcc RdRdy*
Initialization
RC64474/ RC64475 Logic Symbol
VCCOK ColdReset* Reset* ModeClock ModeIn
System Interface Interrupt Interface
April 10, 2001
WrRdy* ExtRqst* Handshake Signals Release* ValidIn* ValidOut*
NMI*
6
Int*(5:0)
Figure 2 Logic Diagram for RC64474/RC64475
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RC64475 208-pin QFP Package Pin-out
Pin names followed by an asterisk (*) are active when low. For maximum flexibility and compatibility with future designs, N.C. pins should be left floating.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Function N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SysAD11 VSS Vcc SysCmd8 SysAD42 SysAD10 SysCmd7 VSS Vcc SysAD41 SysAD9 SysCmd6 SysAD40 VSS Vcc SysAD8 SysCmd5 SysADC4 SysADC0 VSS Vcc SysCmd4 SysAD39 SysAD7 Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Function JTAG32* N.C. N.C. N.C. SysCmd2 SysAD36 SysAD4 SysCmd1 VSS Vcc SysAD35 SysAD3 SysCmd0 SysAD34 VSS Vcc SysAD2 Int5* SysAD33 SysAD1 VSS Vcc Int4* SysAD32 SysAD0 Int3* VSS Vcc Int2* SysAD16 SysAD48 Int1* VSS Pin 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 Function N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SysAD52 ExtRqst* Vcc VSS SysAD21 SysAD53 RdRdy* Modein SysAD22 SysAD54 Vcc VSS Release* SysAD23 SysAD55 NMI* Vcc VSS SysADC2 SysADC6 SysAD24 Vcc VSS SysAD56 Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 Function N.C. N.C. SysAD59 ColdReset* SysAD28 VCC VSS SysAD60 Reset* SysAD29 SysAD61 SysAD30 Vcc VSS SysAD62 SysAD31 SysAD63 Vcc VSS
VccOK
SysADC3 SysADC7 N.C. TDI TRst* TCK TMS TDO
VccP VSSP
MasterClock Vcc VSS
Table 6 RC64475 208-pin QFP Package Pin-Out (Page 1 of 2)
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RC64474TM RC64475TM Pin 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Function SysCmd3 VSS Vcc SysAD38 SysAD6 ModeClock WrRdy* SysAD37 SysAD5 VSS Vcc N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. Pin 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Function Vcc SysAD17 SysAD49 Int0* SysAD18 VSS Vcc SysAD50 ValidIn* SysAD19 SysAD51 VSS Vcc ValidOut* SysAD20 N.C. N.C. N.C. N.C. Pin 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Function SysAD25 SysAD57 N.C. VSS N.C SysAD26 SysAD58 N.C. Vcc VSS SysAD27 N.C. JR_Vcc N.C. N.C. N.C. N.C. N.C. N.C. Pin 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function SysADC5 SysADC1 Vcc VSS SysAD47 SysAD15 SysAD46 Vcc VSS SysAD14 SysAD45 SysAD13 SysAD44 VSS Vcc SysAD12 SysCmdP SysAD43 N.C.
Table 6 RC64475 208-pin QFP Package Pin-Out (Page 2 of 2)
RC64474 128-pin QFP Package Pin-out
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Function JTAG32* SysCmd2 Vcc Vss SysAD5 WrRdy* ModeClock SysAD6 Vcc Vss SysCmd3 SysAd7 SysCmd4 Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 Function Vcc Vss SysAD13 SysAD14 Vss Vcc SysAD15 Vss Vcc SysADC1 Vss Vcc MasterClock Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 Function Vcc SysAD28 ColdReset* SysAD27 Vss Vcc JR_Vcc SysAD26 N.C. Vss N.C. SysAD25 Vss Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 Function Vcc Vss SysAD19 ValidIn* Vcc Vss SysAD18 Int0* SysAD17 Vcc Vss Int1* SysAD16
Table 7 RC64474 128-pin QFP Package Pin-out (Page 1 of 2)
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RC64474TM RC64475TM Pin 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Function Vcc Vss SysAdC0 SysCmd5 SysAD8 Vcc Vss SysCmd6 SysAD9 Vcc Vss SysCCmd7 SysAD10 SysCmd8 Vcc Vss SysAD11 SysCmdP SysAD12 Pin 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Function VssP VccP TDO TMS TCK TRst* TDI Vss SysADC3 VccOK Vss Vcc SysAD31 Vss Vcc SysAD30 SysAD29 Reset* Vss Pin 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Function Vcc SysAD24 SysADC2 Vss Vcc NMI* SysAD23 Release* Vss Vcc SysAD22 Modein RdRdy* SysAD21 Vss Vcc ExtRqst* SysAD20 ValidOut* Pin 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Function Int2* Vcc Vss Int3* SysAD0 Int4* Vcc Vss SysAD1 Int5* SysAD2 Vcc Vss SysCmd0 SysAd3 Vcc Vss SysCmd1 SysAD4
Table 7 RC64474 128-pin QFP Package Pin-out (Page 2 of 2)
Socket Compatibility--RC64474 & RC4640
To ensure socket compatibility between the RC4640 and the RC64474 devices, several pin changes are required, as shown below.
Pin 1 48 49 50 51 52 71 RC4640 N.C Vss Vss Vss Vss Vss N.C. RC64574/ RC64474 JTAG32* TDO TMS TCK TRst* TDI JR_Vcc Compatible to RV4640? Yes. Yes. Yes. Yes. Yes. Yes. Yes. Comments Pin has an internal pull-down, to enable 32-bit scan. Can also be left a N.C. Can be driven with Vss, if JTAG is not needed. Is tristated when TRst* is low. Can be driven with Vss if JTAG is not needed. Can be driven with Vss if JTAG is not needed. Can be driven with Vss if JTAG is not needed. Can be driven with Vss if JTAG is not needed. Can be left N.C. in RC64474, if JTAG is not need. If JTAG is needed, it must be driven to Vcc.
Table 8 RC64574 Socket Compatibility to RC64474 and R4640
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RC64474TM RC64475TM
Socket Compatibility--RC64475 & RC4650
RV4650 32-bit N.C. RC64575 32-bit RC64475 32-bit JTAG32* RV4650 64-bit No Connect RC64575 64-bit RC64475 64-bit JTAG32* Compatible to RV4650? Yes
Pin
Comments
53
In 32-bit, this pin can be left unconnected because of internal pull-down. In 64-bit, this assumes that JTAG will not be used. If using JTAG, this pin must be at Vcc. In RC64475, can be left a N.C, if JTAG is not need. If JTAG is needed, it must be driven to Vcc. If JTAG is not needed, can be left a N.C. If JTAG is not needed, can be left a N.C. If JTAG is not needed, can be left a N.C. If JTAG is not needed, can be left a N.C. If JTAG is not needed, can be left a N.C.
150
N.C.
JR_Vcc
No Connect
JR_Vcc
Yes
180 181 182 183 184
N.C. N.C. N.C. N.C. N.C.
TDI TRsT* TCK TMS TDO
No Connect No Connect No Connect No Connect No Connect
TDO TRsT* TCK TMS TDIO
Yes Yes Yes Yes Yes
Table 9 RC64575 Socket Compatibility to RC64475 & RC4650
Absolute Maximum Ratings Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RC64474/475 3.3V5% Commercial VTERM TC TBIAS TSTG IIN IOUT
1.
Symbol
Rating
RC64474/475 3.3V5% Industrial -0.51 to +4.6 -40 to +85 -55 to +125 -55 to +125 202 503 V C C C mA mA
Unit
Terminal Voltage with respect to GND Operating Temperature(case) Case Temperature Under Bias Storage Temperature DC Input Current DC Output Current
-0.51 to +4.6 0 to +85 -55 to +125 -55 to +125 202 503
VIN minimum = -2.0V for pulse width less than 15ns. VIN should not exceed VCC +0.5 Volts. 2. When VIN < 0V or VIN > VCC 3. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
Recommended Operation Temperature and Supply Voltage
RC64474/475 VCC 3.3V5% 3.3V5%
Grade Commercial Industrial
Temperature 0C to +85C (Case) -40 + 85C (Case)
Gnd 0V 0V
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RC64474TM RC64475TM
DC Electrical Characteristics
Commercial Temperature Range--RC64474/64475 (VCC = 3.35%, TCASE = 0C to +85C)
RC64474/RC64475 180MHz Minimum VOL VOH VOL VOH VIL VIH IIN CIN COUT I/OLEAK -- VCC - 0.1V -- 2.4V -0.5V 2.0V -- -- -- -- Maximum 0.1V -- 0.4V -- 0.2VCC VCC + 0.5V 10uA 10pF 10pF 20uA RC64474/RC64475 200MHz Minimum -- VCC - 0.1V -- 2.4V -0.5V 0.7VCC -- -- -- -- Maximum 0.1V -- 0.4V -- 0.2VCC VCC + 0.5V 10uA 10pF 10pF 20uA RC64474/RC64475 250MHz Minimum -- VCC - 0.1V -- 2.4V -0.5V 2.0V -- -- -- -- Maximum 0.1V -- 0.4V -- 0.2VCC VCC + 0.5V 10uA 10pF 10pF 20uA -- -- 0 VIN VCC -- -- Input/Output Leakage |IOUT|= 4mA |IOUT|= 20uA
Parameter
Conditions
Power Consumption--RC64474
.
Parameter System Condition: ICC standby
RC64474 180MHz Typical1 180/90MHz -- -- 530 mA2 630mA2 60 mA2 110 mA2 630 mA2 750 mA2 Max
RC64474 200MHz Typical1 200/100MHz -- -- 600mA2 700 mA2 60 mA2 110 mA2 700 mA2 850 mA2 Max
RC64474 250MHz Typical1 250/125MHz -- -- 700 mA2 850mA2 100 mA2 110 mA2 850mA2 1000mA2 Max --
Conditions
CL = 0pF3 CL = 50pF CL = 0pF No SysAd activity3 CL = 50pF R4x00 compatible writes, TC = 25oC CL = 50pF Pipelined writes or write re-issue, TC = 25oC3
active
750 mA2
1050 mA4
850 mA2
1200 mA4
1000mA2
1400mA2
1. 2.
Typical integer instruction mix and cache miss rates These are not tested. They are the results of engineering analysis and are provided for reference only 3. Guaranteed by design. 4. These are the specifications IDT tests to insure compliance.
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RC64474TM RC64475TM
Power Consumption--RC64475
Parameter System Condition: ICC standby active, 64-bit bus option4 RC64475 180MHz Typical1 180/90MHz -- -- 720 mA2 850 mA2 60 mA
2
RC64475 200MHz Typical1 200/100MHz -- -- 850 mA2 1000 mA2 60 mA
2
RC64475 250MHz Typical1 250/125MHz -- -- 935 mA2 1100mA2 100 mA
2
Max
Max
Max --
Conditions
CL = 0pF3 CL = 50pF CL = 0pF No SysAd activity3 CL = 50pF R4x00 compatible writes, TC = 25oC CL = 50pF Pipelined writes or write re-issue, TC = 25oC3
110 m2A 850 mA2 1000 mA2
110 mA2 1000 mA2 1200 mA2
110 mA2 1100 mA2 1360mA2
1000 mA2
1200 mA5
1200 mA2
1400 mA5
1360 mA2
1600 mA2
1. Typical integer instruction mix 2.
and cache miss rates These are not tested. They are the results of engineering analysis and are provided for reference only. 3. Guaranteed by design. 4. In 32-bit bus option, use RC64474 power consumption values. 5. These are the specifications IDT tests to insure compliance.
Timing Characteristics--RC64474/RC64475
Cycle MasterClock tMCkHigh tMCkLow tMCkP 1 2 3 4
SysAD,SysCmd Driven SysADC
D tDM tDO
D tDOH
D
SysAD,SysCmd Received SysADC
D tDS tDH
D
D
D
Control Signal CPU driven ValidOut* Release* Control Signal CPU received RdRdy* WrRdy* ExtRqst* ValidIn* NMI* Int*(5:0)
* = active low signal
tDO tDOH
tDS
tDH
Figure 3 System Clocks Data Setup, Output, and Hold Timing
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RC64474TM RC64475TM
tTCK TCK t5 t1 t2
t3
TDI/ TMS tDS TDO TDO tDO
Notes to diagram: t1 = tTCKlow t2 = tTCKHIGH t3 = tTCKFALL t4 = TRST (reset pulse width) t5 = tTCKRise
tDH TDO
TRST*
t4
> = 25 ns
Figure 4 Standard JTAG timing
AC Electrical Characteristics
Commercial Temperature Range RC64474/RC64475 (VCC=3.3V 5%; TCASE = 0xC to +85C) Clock Parameters
Parameter1 Pipeline clock Frequency MasterClock HIGH MasterClock LOW MasterClock Frequency MasterClock Period Clock Jitter for MasterClock MasterClock Rise Time MasterClock Fall Time ModeClock Period JTAG Clock Input JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time Symbol PClk tMCHIGH tMCLOW
--
Test Conditions
RC64474/ RC64475 RC64474/ RC64475 RC64474/ RC64475 180MHz 200MHz 250MHz Units Min 80 Max 180 -- -- 90 100 250 2.5 2.5
t
Min 80 3 3 10 10 -- -- -- -- 100 40 40 -- --
Max 200 -- -- 100 100 250 2 2
t
Min 80 2.5 2.5 10 8 -- -- -- -- 100 40 40 -- --
Max 250 -- -- 125 100 250 2 2
t
MHz ns ns MHz ns ps ns ns ns ns ns ns ns ns
Transition 3ns Transition 3ns -- -- -- -- -- -- -- -- -- -- --
3 3 10 11.1 -- -- -- -- 100 40 40 -- --
tMCP tJitterIn tMCRise tMCFall
tModeCKP
256*
MCP
256* MCP
256*
MCP
tTCK tTCKHIGH tTCKLOW tTCKRise tTCKFall
-- -- -- 5 5
-- -- -- 5 5
-- -- -- 5 5
1. Timings are measured from 1.5V of
the clock to 1.5V of the signal.
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RC64474TM RC64475TM
Capacitive Load Deration--RC64474/RC64475
Test Conditions -- 180MHz Min -- Max 2 200MHz Min -- Max 2 250MHz Min -- Max 2
Parameter Load Derate
Symbol CLD
Units ns/25pF
System Interface Parameters Note: Operation of the RC64474/RC64475 is only guaranteed with the Phase Lock Loop enabled.
RC64474/ RC64475 Parameter1 Symbol Test Conditions 180MHz Min Data Output2 tDM= Min tDO = Max mode14..13 = 10 mode14..13 = 11 mode14..13 = 00 mode14..13 = 01 Data Output Hold tDOH4 mode14..13 = 10 mode14..13 = 11 mode14..13 = 00 mode14..13 = 01 Input Data Setup Input Data Hold
1.
RC64474/ RC64475 200MHz Min 03 03 -- -- 03 03 03 03 2 1.0 Max 5 5 9 9 -- -- -- -- -- --
RC64474/ RC64475 250MHz Min 03 03 -- -- 03 03 03 03 2 1.0 Max 4.7 4.7 7 7 -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns Units
Max 6 6 9 9 -- -- -- -- -- --
03 03 -- -- 03 03 03 03 2 1.0
tDS tDH
trise = 5ns tfall = 5ns
Timings are measured from 1.5V of the clock to 1.5V of the signal. 2. Capacitive load for all output timings is 50pF. 3. Guaranteed by design. 4. 50pf loading on external output signals, fastest settings. Also applies to JTAG signals (TRST*,TDO,TDI,TMS)
Boot-Time Interface Parameters
RC64474/ RC64475 Parameter Symbol 180 MHz Min Mode Data Setup Mode Data Hold tDS tDH 3 0 Max -- -- RC64474/ RC64475 200 MHz Min 3 0 Max -- -- RC64474/ RC64475 250MHz Min 3 0 Max -- -- Master Clock Cycle Master Clock Cycle Units
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RC64474TM RC64475TM
Mode Configuration Interface Reset Sequence
Vcc
MasterClock
2.3V 2.3V
(MClk)
> 100ms
TDS 256 MClk cycles 256 MClk cycles
VCCOK
ModeClock TMDS TMDH Bit 0 TDS ColdReset* TDS > 64K MClk cycles > 64 MClk cycles TDS Bit 1 Bit 255 TDS
ModeIn
Reset*
Figure 5 Power-on Reset
Vcc
Master Clock
(MClk)
VCCOK
TDS > 100ms
TDS 256 MClk cycles 256 MClk cycles
ModeClock TMDS Bit 0 TDS ColdReset* TDS > 64K MClk cycles > 64 MClk cycles TDS TMDH Bit Bit 1 255 TDS
ModeIn
Reset*
Figure 6 Cold Reset
Vcc
Master Clock
(MClk)
VCCOK 256 MClk cycles
ModeClock
ModeIn
ColdReset* TDS TDS > 64 MClk cycles
Reset*
Figure 7 Warm Reset
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RC64474TM RC64475TM
1.5V
50 RC64474/RC64475 Output
.
50
Signal All Signals
Equivalent Limp Capacitance 25 pF
Figure 8 Output Loading for AC Timing
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RC64474TM RC64475TM
RC64475 Physical Specifications
The RC64475 is available in a 208-pin power quad (PQUAD) package.
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RC64474TM RC64475TM
RC64475 208-pin Package (page 2)
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RC64474TM RC64475TM
RC64474 128-Pin Package (Page 1 of 3)
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RC64474TM RC64475TM
RC64474 128-pin Package (page 2 of 3)
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RC64474TM RC64475TM
RC64474 128-pin Package (Page 3 of 3)
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RC64474TM RC64475TM
Ordering Information
IDT79RCXX Product Type YY Operating Voltage XXXX Device Type 999 Speed A Package A Temp range/ Process
Blank I
Commercial Temperature (0C to +85C Case) Industrial Temperature (-40C to +85C Case)
DZ DP 180 200 250 474 475
128-pin QFP 208-pin QFP 180 MHz PClk 200 MHz PClk 250 MHz PClk Embedded Processor
V 79RC64
3.3V +/-5% 64-bit Embedded Microprocessor
Valid combinations
IDT79RC64V474 - 180, 200, 250 DZ IDT79RC64V475 - 180, 200, 250 DP IDT79RC64V474 - 180, 200, 250 DZI IDT79RC64V475 - 180, 200, 250 DPI 128-pin QFP package, Commercial Temperature 208-pin QFP package, Commercial Temperature 128-pin QFP package, Industrial Temperature 208-pin QFP package, Industrial Temperature
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com
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for Tech Support: email: rischelp@idt.com phone: 408-284-8208
The IDT logo is a trademark of Integrated Device Technology, Inc.
April 10, 2001

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